Multi-Layer Package Power/Ground Planes Synthesis with Balanced DC IR Drops: A Game-Theoretic Optimization Approach

Recently, the challenge of integrating an increasing number of transistors on a single die to adhere to Moore’s Law has spurred the need for innovative packaging solutions. Power/ground planes are integral to packages, and designers typically strive to maximize their size. This provides shielding and maintains constant impedance for adjacent high-speed signal wires, benefiting signal integrity. Additionally, large power/ground planes help reduce DC IR drops, enhancing power integrity. However, the necessity for multiple power/ground nets, each requiring independent power/ground planes within a package, makes the optimal allocation of limited free space a complex task. In this paper, we introduce a game-theoretic optimization method aimed at evenly mitigating DC IR drops across the multi-layer package power/ground planes. In the formulated game of achieving the ideal power/ground plane design, we can enhance the use of package space and realize a design with evenly distributed DC IR drops across all power/ground planes. This is accomplished by adjusting strategies and reaching a state of Nash equilibrium in the allocation of free space. Additionally, we propose a rapid multi-layer power/ground plane DC IR drop evaluation and a power/ground plane legalization method to bolster our optimization method.