FlexiCTS: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs

Face-to-Face (F2F) 3D ICs enable advanced vertical integration but pose critical challenges for clock tree synthesis (CTS). Existing pseudo-3D flows rigidly partition clock paths across dies, fragmenting common paths and crippling Common Path Pessimism Removal (CPPR), resulting in excessive skew and inefficient hybrid bonding terminal (HBT) utilization.

We present FlexiCTS, a correct-by-construction CPPR-aware framework featuring adaptive cross-die buffer assignment to maximize path sharing and optimize HBT allocation. Unlike existing approaches that either partition ports or centralize buffers on a single die, FlexiCTS builds a unified clock tree with buffers placed across both dies, enabling cross-die common clock paths that unlock substantial CPPR benefits.

Experimental results show that FlexiCTS achieves 4.1× skew reduction and 88% fewer HBTs than state-of-the-art methods, while simultaneously matching 2D timing quality with superior resource efficiency.