BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs

Published in The 63rd ACM/IEEE Design Automation Conference (DAC), 2026

Recommended citation: L.L. Jin, H.Y. Xu, S.Y. Liang, Z. Zhuang, Z. Hu, Z.X. Wang, B. Yu, R.M. Chen, T.-Y. Ho, "BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs," The 63rd ACM/IEEE Design Automation Conference (DAC), 2026.

Backside power delivery networks (BSPDN) provide superior power integrity while freeing backside routing resources. However, existing works fail to fully exploit these resources for power, performance, and area (PPA) optimization through strategic net allocation.

This paper presents BSPDN-Elite, a comprehensive co-optimization framework that maximizes PPA by strategically routing both clock and signal nets on the backside, enabling double-side routing. Our approach integrates three key innovations: (1) an importance-weighted graph classification method for double-side routing selection that addresses signal integrity issues by leveraging PDN structures as natural shields; (2) backside-aware cell placement techniques that reposition driver and load cells to minimize Design Rule Check (DRC) violations and improve routing quality; and (3) adaptive BSPDN refinement that fills remaining backside resources with power stripes to further reduce IR-drop.

Experimental results demonstrate 88.1% IR-drop reduction, 23.0% frequency improvement, 10.9% power savings, and significant timing improvements (66.3% WNS, 40.2% TNS) over conventional frontside PDN designs with negligible nTSV overhead.